Prior programmable memories have been implemented using split-gate non-volatile memory (NVM) cells. These programmable memories can be implemented as stand-alone memory integrated circuits or can be embedded within other integrated circuits, as desired.
FIG. 1 (Prior Art) is a diagram of an embodiment for a split-gate non-volatile memory (NVM) cell 100. As depicted, the split-gate NVM cell 100 includes a semiconductor substrate 112, a drain 136, a source 138, a lightly doped channel region 126, a select gate 116 and a control gate 134. Layer 114 is a select-gate dielectric layer. Layer 128 is a control-gate dielectric layer and also provides a gap dielectric layer between the select gate 116 and the control gate 134. Layer 118 is an antireflective coating (ARC). And layer 132 is a discrete charge storage layer for the split-gate memory cell.
FIG. 2 (Prior Art) is a voltage control diagram 200 for read and erase operations for the split-gate NVM cell 100 using positive bias (+BIAS). During a read operation, the drain voltage (VD) is set to 0.5 volts, and the source voltage (VS) is set to 0 volts, which can represent ground for the integrated circuit within which the split-gate NVM cell 100 is integrated. Also during a read operation, the select-gate voltage (VSG) and the control-gate voltage (VCG) are set to a selected read voltage level (VR), which can be, for example, the supply voltage (VDD) for the integrated circuit within which the split-gate NVM cell 100 is integrated. During an erase operation, the drain voltage (VD) and the source voltage (VS) are set to 0 volts. Also during an erase operation, the select-gate voltage (VSG) is typically set to the read voltage level (VR) or to 0 volts (e.g., ground) as convenient and available voltages, and the control-gate voltage (VCG) is set to a positive erase voltage (VE), which is a large positive voltage used to remove charge from the discrete charge storage layer 132 for the erase operation. As one example, it is noted that 1.2 volts can be selected for the read voltage level (VR), and 14 volts can be selected for the erase voltage (VE).
FIG. 3 (Prior Art) is a voltage control diagram 300 for read and erase operations for the split-gate NVM cell 100 using negative bias (−BIAS). During a read operation, the drain voltage (VD) is set to 0.5 volts, and the source voltage (VS) is set to 0 volts. Also during a read operation, the select-gate voltage (VSG) and the control-gate voltage (VCG) are set to a selected read voltage level (VR). During an erase operation, the drain voltage (VD) and the source voltage (VS) are set to 0 volts. Also during an erase operation, the select-gate voltage (VSG) is typically set to 0 volts (e.g., ground) or to the read voltage level (VR) as convenient and available voltages, and the control-gate voltage (VCG) is set to a negative erase voltage (−VE), which is a large negative voltage used to remove charge from the discrete charge storage layer 132 for the erase operation. As one example, it is noted that 1.2 volts can be selected for the read voltage level (VR), and −14 volts can be selected for the erase voltage (−VE).
During erase operations for an array of split-gate NVM cells 100, select-gate to control-gate break-down failures can occur. One prior solution to reduce these break-down failures is to increase the thickness of the gap dielectric layer between the control gate 134 and the select gate 116. Controlling this gap thickness, however, can be difficult for some split-gate NVM cell processes. For example, the dielectric layer 128 in FIG. 1 (Prior Art) provides an insulated gap between the control gate 134 and the select gate 116 and provides the control gate dielectric layer between the control gate 134 and the lightly doped channel region 126. As this dielectric layer 128 is formed in one or more common processing steps, the gap thickness will be determined by the control gate stack requirements and is not easily adjusted without adversely affecting the operation of the gate stack. One prior solution to this gate stack requirement is to add an additional processing step to add a gap spacer oxide layer between the select gate 116 and the control gate 134 prior to formation of the control gate dielectric layer 128.